In modern digital systems,SRAM(Static Random Access Memory)has become the core choice of data buffering and caching because of its high speed and no need to refresh.Especially in CPU,SRAM is often used as a first-level or second-level cache to match the speed difference between processor and main memory.With the continuous evolution of integrated circuit technology,the memory cell area of embedded SRAM is shrinking at a rate of about 0.5 times per generation-for example,its storage density can reach 150 MB/cm at 45nm nodes.In the sram family,dual-port SRAM(DP-SRAM)can access data at the same time because it has two independent read and write ports.Dual-port SRAM plays an irreplaceable role in multi-core processors,real-time signal processing and other systems that require strict bandwidth and parallelism.
 

Traditional SRAM(Single-Port SRAM has only one set of address lines,data lines and control lines,which means that only read or write operations can be performed at the same time.Dual port sram provides two sets of completely independent bus interfaces.Dual port sram allows two different systems(or two modules of the same system)to access the memory at the same time-one port can read,the other port can write,or even two ports can perform read operations at the same time(depending on the specific architecture).The"shared multi-port"design of dual-port sram makes data exchange without external bus arbitration,which greatly reduces the system delay.
 

From the memory cell structure,dual-port sram is usually based on the classic six-transistor CMOS cell,which is realized by copying and adding a set of read-write control circuits.Different from the simple dual port of"one read and one write(1R1W)",the real dual port(i.e.true dual port)supports both read and write operations,so it is also called"two read and write(2RW)"unit.This design brings spatial parallelism:two ports can respond to different read and write requests at the same time,which is especially suitable for high throughput scenes such as video codec and network packet processing.

Keywords:Dual port sram